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Media processing architecture scales from MP3 to HD video
A heterogeneous, multicore approach: multiple high-performance processors are connected to multiple SIMD processors and multiple DMA engines, and are complemented with domain-specific accelerators, all interconnected with low-overhead, low-latency active communications channels and local wide data buses.
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By
Marco Jacobs
ARC International
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Page 1 of 5
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Video Imaging DesignLine
(03/09/2007 3:20 AM EST)
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The landscape for multimedia devices varies widely: from sub-$20 MP3 players for kids to almost theatre-sized flat-panel displays for the home. Displaying images on a modern TV means decoding an HD- resolution H.264 bit stream, which demands three orders of magnitude more computational horsepower than decoding an MP3 file. Another example of this processing disparity is a camera phone versus a camcorder. The phone typically captures video in a QCIF (176x144) format, whereas camcorders on the market today capture video in the HD MPEG-2 format. These formats demand widely different amounts of processing performance from the devices' video subsystems. For SoC designers it's a big benefit that their underlying media processing architecture stays the same. If not, redesigns are required to address each design point in this wide range of applications, resulting in higher SoC design costs and longer times to market.
Consumers want to play and share content across a variety of devices. Most people already own several media-enabled devices: televisions, set-top boxes, DVD players, mobile phones, PCs, portable media players, etc. An important capability for future devices will be to stream and/or move content between these devices. Very different devices need to be interoperable. Since there are many audio and video coding standards in use, interoperability requires the underlying media architecture to be programmable. Coding standards are then programmed in software, yielding a flexible and upgradeable end device.
Programmability also means that the key algorithms affecting audio and image quality can be upgraded -- a desirable feature, since research engineers constantly develop new methods for increasing the quality of the images or sound, and it is the audio and picture quality that differentiates the product from the competition. Programmability also allows the device manufacturer to further differentiate its product, to use the SoC in many different ways, to reduce the risk of silicon respins, and to lengthen the product's market life.
As a result, media processing architectures must span a huge range of complexity and must be software-programmable. The ARC VRaptor Architecture takes a heterogeneous, multicore approach: multiple high-performance processors are connected to multiple SIMD processors and multiple DMA engines, and are complemented with domain-specific accelerators, all interconnected with low-overhead, low-latency active communications channels and local wide data buses.
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Figure 1: ARC VRaptor Media Architecture
Next: Parallel media processing
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