Manhasset, N.Y. -- The scientists and engineers who gather in San Francisco this week for the International Solid-State Circuits Conference will hear conflicting forecasts for CMOS. As the technology edges closer to its assumed atomistic and quantum-mechanical boundaries, pundits are pushing nanotechnology, bioelectronics and quantum computing as urgently needed replacements.
Nonetheless, as some ISSCC technical presentations will attest, circuit designers are tweaking CMOS and leveraging new materials to ensure at least another 10 years of CMOS service.
Power dissipation and processvariability continue to preoccupy researchers as first-order concerns in design. At the architectural level, initiatives such as self-healing systems, self-biasing substrates, and simultaneous circuit and device diagnostics will extend a circuit's ability to survive and function given a wider range of sensitivities. The bottom line is that the development of silicon technology will still be driven by system needs.
As the silicon industry moves toward the 45-nanometer node and beyond, circuit/technology co-design, with architectures developed concurrently with device innovations, will solve the challenges of deep-submicron CMOS, Tze-Chaing (T.C.) Chen, IBM fellow and vice president of science and technology, will predict in his plenary presentation.
Hermann Eul, a member of the management board at Infineon Technologies, will observe in his plenary address that while devices are being fabricated using processes managed at the atomic level, IC design involves detailed systems engineering. This is especially true in communications applications, where data- rate and mobility trade-offs and proliferating standards are creating an urgent need to cope with the coexistence of divergent technologies. Eul will explore how R&D engineers bridge system-level, silicon and software design.
In the MPU session, Sun Microsystems Inc. will detail its first-generation Niagara Sparc processors, which implement a power-efficient multithreading architecture to achieve high throughput with minimum hardware complexity. The design combines eight four-threaded 64-bit cores, a high-bandwidth crossbar, a shared 3-Mbyte L2 cache and four DDR2 DRAM interfaces. Cavium Networks Inc. will preview a multicore RISC processor that integrates security engines and network function accelerators to create a high-performance, power-efficient system-on-chip. It contains 180 million transistors, dissipates 25 watts at 600 MHz and is fabricated in a 1.2-volt, 0.13-micron CMOS process.
Intel Corp. will detail a dual-core 64-bit Xeon processor implemented in a 65-nm process. The die has 1.328 billion transistors. Archrival AMD Inc. will talk about a microprocessor with two Hammer cores and an on-chip DDR2 memory controller fabricated in a 90-nm silicon-on-insulator process. The chip achieves a clock frequency of 2.6 GHz at 1.35 V while dissipating 95 W. IBM Corp. will present a pair of Power-architecture 64-bit processors built in 90-nm dual strained-silicon SOI technology, while Fujitsu Microelectronics will show an ambitious 170-Gbit/s crossbar architecture for a multiprocessor server.
