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H.264 encoder design using Application Engine Synthesis
The goal was to build an H.264 video encoder that would meet real-time requirements of 30 frames per second at D1 resolution with completion in less than 5 months.
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By
Craig Gleason
Synfora, Inc.
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Page 1 of 6
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Video Imaging DesignLine
(05/09/2008 3:00 AM EDT)
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System on Chip design is driven by complex consumer devices that rely on standard algorithms such as H.264, WiMax, or JPEG for their defining capabilities. These reference standards allow room for innovative implementation that result in differentiated products.
Designing these SoCs is an enormous undertaking, with significant cost and risk associated with each project. One way to reduce both project cost and schedule risk is to use Application Engine Synthesis (AES) for the automatic creation of an application engine such as an H.264 encoder from a sequential, untimed C algorithm.
The goal of the project described in this article was to emulate a typical design process for an H.264 encoder and to determine AES's ability to generate efficient hardware designs for real-life, high-complexity applications, while also demonstrating significant savings in terms of time and cost (of resources). We set the target of building an H.264 encoder for D1 size video that would meet real-time requirements (30 frames per second) on the most stringent test sequences, and aimed to complete the project in less than 5 months.
This article describes the process used, targets met, and productivity gains achieved.
Figure 1: In a consumer SoC, complex application engines consume significant design and verification time. Other components rarely change.
The role of application engines
A typical SoC designed for a consumer device comprises various kinds of IP. At the highest level, there are four different types of IP:
- Complex application engines (e.g., video codecs, modems): These define the functionality of the product, and change rapidly with each revision. This type of IP is based on reference algorithms that are already in C and that are designed by architects who work in C.
- Star IP such as CPUs and DSPs: This is usually hand-crafted, built bottom-up, needs significant investment, and doesn't change often.
- Connectivity and Control IP such as USB and DMA: This type of IP never defines the functionality nor differentiates the end product. Sometimes, it needs a limited amount of tailoring.
- Memory: This takes up the largest amount of area, but also neither defines the function nor differentiates the end product. Memories are almost always compiled and built bottom-up.
Typically, the bulk of engineering effort is in designing and verifying complex application engines. These are complex pieces of IP and are usually subdivided into many blocks. Depending on the application, an engine may consist of a control processor and one or more hardware accelerators that help to meet design objectives such as cost, performance, and power.
Next: Building the application engines
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