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Multi-channel surveillance DVR design
How a video encoder can be designed to leverage the extra cycles provided by hardware accelerators.
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By
Shinjan Tiwary
Engineer in Video Technology Solutions,
Ittiam Systems
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Page 1 of 6
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Video Imaging DesignLine
(08/29/2008 3:00 AM EDT)
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Digital video recorders (DVRs) have been used as an integral part of set-top boxes after their launch in CES, 1999. DVRs are primarily time shifting devices, used to record entertainment content like movies and favorite TV shows. If used personally, expectations from such devices are multi-format, real-time encode which could be played later in time or shared with others. If used commercially real-time multi-channel encoding capacity for such a recorder becomes a primary goal, so that the overall BOM (Bill-Of-Materials) can be reduced.
Surveillance system DVRs
When used in a surveillance scenario, place shifting capabilities are also expected from DVRs. Compressed data being stored on hard drives is streamed to a remote point for monitoring or analytics. This presses extra constraints of low delay encoding, which further disallows multi-pass encoding, posing significant challenges to compression quality. Encoders in such applications should support encoding of various resolutions. Detailed video (for example D-1) could be used for monitoring and a smaller resolution (e.g. SIF/CIF) could be used for storage to conserve space. A surveillance eco-system has encoder and analytics block working in cohesion. Hence, encoders have to provide analytics data and should be designed to take directions from such a block to support ROI (Region of Interest) encoding.
Such a surveillance application based DVR needs to be installed at different locations in buildings where multiple inputs from various PTZ (pan-tilt-zoom) cameras can be tapped, compressed and are sent over an Ethernet link to storage racks and a central point of monitoring. Figure 1, depicts such a surveillance DVR system.
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Figure 1: Surveillance Eco-System
ASIC vs. DSP
Once we are clear about the requirement needs posed by such a system, we need to make a choice of implementation platform. ASIC offers low power solutions for encoders and other analytics engine but lacks the flexibility of programming it once the design is frozen. It is highly desirable that intelligent algorithms in such a system be continuously tweaked to suit an environment. Algorithms like rate control algorithm and object detection routine are continuously trained depending on various conditions. ASIC solutions cannot cater to such changing needs. Embedded systems due to their configurability, low time to market, scalability and probably lowest BOM cost, offer the best technology for designing such surveillance systems.
A few years back, available DSPs (digital signal processors) didn't have enough horsepower to support multi-channel encoding on a single chip. This required each camera to be fitted with its own individual compression engine, thereby increasing the overall cost. With the recent convergence of SoC and DSP, many processors are now coming with their own hardware accelerators. This has enabled DSPs to fit multiple channels of compression on a single chip. The next section presents how a video encoder can be designed to leverage the extra cycles provided by hardware accelerators. Further we will also look into some of the system requirements for multiple encoders to interact flawlessly with the network interface.
Next: Encoder design: architectural considerations
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