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Image processing is a challenging discipline: high processing power is required to calculate image adjustments in real-time. Since the standards by which a qualitative picture is measured by are relative, experts have to face a serious debate, as defining the quality of an image still lies in the eye of the beholder.
Pictor image processing aims at providing adjustable high-quality images. The programmable features of Pictor mean a major step forward compared to other non-programmable image processing solutions which are currently offered on the market.
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Maximum output through parallelism
Pictor is designed for real time image processing. It supports HD resolutions including 1080i. The core of the programmable platform is the VSP. The VSP, explained in detail in the next section, is made for digital signal processing applications and has high processing power and an equivalently high data bandwidth with low power usage. The image processor has a VLIW fixed-point arithmetic architecture and consists of parallel processing units (slices). Pictor has -- in comparison to the Video VSP used in the Scaleable Video Engine (SVEN) -- slices with separate quad data paths. The architecture of Pictor can, therefore, achieve a processing power of approximately 176 in complex giga-operations at only 230 MHz.
In addition, Pictor comes with special instructions including: SAD (SUM of Absolute Difference) and minimum-maximum search, which supports calculations in only one clock cycle. All image-processing algorithms are software implemented without requiring an additional hardware accelerator.
Libraries complement the platform
Additionally ODM offer tailored libraries for digital image processing (DIP).
In general, the algorithms of DIP can be applied on a wide range of applications that has to be covered by engineers with very different backgrounds such as digital TVs, cameras, and surveillance. The DIP theory is based on calculation models, which, in turn, challenge the user to grasp the subjective cognition and the multidisciplinary relations of computer graphics and optical characteristics. By introducing Pictor, On Demand Microelectronics managed to provide a solution for these multidimensional tasks.
The VSP Processor Core
The Vector Signal Processor core is a synthesizable core that can be configured and scaled to add processing power. The core is designed specifically to address embedded System-on-Chip (SoC) applications. The configurable and scalable architecture enables engineers to design a custom-made solution to match the application requirements for the target SoC designs.
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The VSP is a scalable VLIW architecture that allows the designer to mould the architecture to the processing power needs of the application. The memory bandwidth is automatically scaled along with the number of slices because each slice has two local data memories. The designer can treat this data memory as registers as it is possible to read and write in one cycle.
The designer can also configure the width of the datapath to suit the accuracy of the application. Another advantage of this SIMD aswell as MIMD architecture is that algorithms that can be vectorised can run unchanged on different number of slices. A suitable example in this case would be a FIR filter calculation.
The slices within a VSP have two communication means. The streamline bus allows slices to feed the neighbouring slices with input data and the crossbar allows the output registers of the slices to be the input register of any other slice. This is useful for algorithms such as Fast Fourier Transform. To reduce the programming overhead of the slices and maximize the advantages of the communication means between slices, there is a sequencer that ensures that the slices are tightly coupled to another and therefore are automatically synchronous. This synchronous mechanism allows the global arithmetic unit to do fast operations on synchronous partial results from the slices. This is useful when for example performing the final addition or performing minimum search with the partial results from the slices.
The instruction used by the VSP is a VLIW. This VLIW can either be a SIMD instruction or a MIMD instruction. When using a SIMD instruction, code compression ensures that the instruction VLIW is shortened to the minimum size required for the instruction. This feature optimizes the code memory. If the engineer may wish to optimize the size of the core, then a profiler may be used to reduce the area to the size of dedicated hardware. This is done by removing not used instructions or making changes to memory.
Other key features of this architecture includes 6 address generators performing the typical types of DSP addressing, an IEEE rounding unit, maximum 80 bit accumulator, zero overhead HW loops or support plug-ins such as Viterbi. This core is offered with an extensive development platform, which includes a development board, software platform, a comprehensive DSP-algorithm library and configuration tools. All features having in common to give the engineer this additional edge when designing a product.
Next: VSP Applications
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